CoreMultiplier

- multiplies functionality of cores, bus-systems and
complete subdesigns with reduced area
- uses hyper pipelining technique 
- reads RTL (SystemVerilog, Verilog, VHDL)
- timing estimation and register insertion on RTL
- writes modified RTL !!!
- works for FPGA and ASIC technologies

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Timing Driven RTL2RTL Partitioner

- design partitioner tool for system prototyping
- full or semi automatic timing driven partitioning
- enables super fast incremental synthesis
- reads RTL (SystemVerilog, Verilog, VHDL)
- timing estimation and partitioning on RTL
- writes modified RTL !!!
- supports switch-routing based systems

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System - Prototyping - Emulator hardware SPE Gen2

- uses latest Altera and/or Xilinx devices
- supports 1..7 devices, FPGA-wise extendable
- new: PCIe Gen2 x8 connection to system CPU
- new: two 4GB DDR3 SDRAMs on each FPGA board
- supports FPGAs with 1200 user-ios
- unlimited routing capabilities
- 108MHz w.c. system-performance (reg. to reg.)
- 333MHz wave pipelining btw. all FPGA IOs
- 1/4 of FPGA IOs directly accessible (no switch)
- bank voltage for ext. logic can be driven from ext.
- SCEMI compatible

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